1. Field of the Invention
This invention generally relates to multicore processing systems, and more specifically, to digital frequency clocking in multicore processor systems. Even more specifically, in the preferred embodiment, the invention relates to digital multi-frequency clocking in multi-chip/multi-core processors.
2. Background Art
Servers are beginning to exploit a multiplicity of multi-core processor chips in order to continue to increase performance, as processor frequency scaling can no longer meet the industry growth in performance. Also, the increasing difficulty and hardware cost, as well as signal integrity concerns, associated with the transmission of high frequency clocking throughout a multi-chip and multi-core processor server make high frequency clocking an untenable long-term strategy for future server systems. The state of the art for clock distribution is based on analog signals using transmission lines. This technique is limited in scalability due to skin effect, media and connector loss, crosstalk, termination mismatches, etc. Today's large servers contain, for example, greater than 10 processor chips typically containing two cores per chip. It is expected both chips and cores per chip will increase in future servers. Transmission of high frequency clocks (>5-10 GHz) for multiple chips, with multiple cores per chip, server systems are not feasible with known carriers for electronic packages and electrical connectors. The need to operate this configuration in a tightly coupled mode as a Symmetric Multi-processor (SMP) will require a new clocking paradigm.
In view of the above, a novel approach is needed to provide processor clocking in future generations of multiple multi-core processor chip servers and computing platforms.